1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and, more particularly, to a method of fabricating a field effect transistor (FET) with an LDD structure which has a gate electrode containing high melting-point metal silicide such as polycide.
2. Description of the Related Art
To begin with, a method of a polycrystalline silicon gate electrode IGFET will be discussed. This method is described in, for example, International Electron Device Meeting (IEDM) Technical Digest, 1981, pp 651-654.
As shown in FIG. 1A, a device-forming area is formed on a P type silicon semiconductor substrate 1 by a field oxide film 2. A gate oxide film 3 is formed on the device-forming area on the substrate 1, and a gate electrode 4 formed of a polycrystalline silicon film is patterned on the gate oxide film 3.
Next, with the gate electrode 4 as a mask, first impurity ions are injected into the surface of the substrate 1 to form an N.sup.- type source and drain region 5 in the surface of the substrate 1, as shown in FIG. 1B.
Then, a silicon oxide film 6 is deposited on the entire surface of the resultant structure by chemical vapor deposition as shown in FIG. 1C.
Subsequently, anisotropic dry etching is performed on this silicon oxide film 6 to form an insulating spacer 7 on the side wall of the gate electrode 4 as shown in FIG. 1D.
Then, as shown in FIG. 1E, with the gate electrode 4 and insulating spacer 7 used as masks, second impurity ions are injected in the surface of the substrate 1 at a higher concentration than the first impurity ions, thus forming a high-concentration ion injection region 8.
Next, as shown in FIG. 1F, thermal oxidation is carried out to form an N.sup.+ type source and drain region 8a from the high-concentration ion injection region 8 and form a thermal oxide film 9b on this source and drain region 8a. This thermal oxidation also forms a thermal oxide film 9a on the gate electrode 4.
According to this prior art, a heat treatment is performed in the oxide atmosphere in order to form the N.sup.+ type source and drain region 8a, but the impurity diffusion speed is faster than the speed of the heat treatment in the inactive gas. This heat treatment in such an oxide atmosphere therefore becomes inappropriate to miniaturize transistors and improve the high integration thereof.
As a solution to this shortcoming, the order of the injection of the second and thermal oxidation is reversed in such a way that after the insulating spacer 7 is formed, thermal oxidation is performed to form the thermal oxide films 9a and 9b as shown in FIG. 2A, after which the second impurity ions are injected into the surface of the substrate 1 and a heat treatment is then carried out in the inactive gas to form the N.sup.+ type source and drain region 8b, as shown in FIG. 2B.
An LDD-IGFET having a polycide gate electrode is formed in conformity to the method of fabricating an LDD-IGFET having a polycrystalline silicon gate electrode.
This will be discussed below more specifically. As shown in FIG. 3A, a polycrystalline silicon film 11 and tungsten silicide film 12 are stacked on a gate oxide film 3 and this stacked films are patterned to form a gate electrode 10.
Then, first impurity ions are injected into the surface of the substrate 1 to form an N.sup.- type source and drain region 5, as shown in FIG. 3B.
Then, a silicon oxide film 6 is deposited on the entire surface of the resultant structure as shown in FIG. 3C.
Anisotropic etching is then performed to form an insulating spacer 7 on the side wall of the gate electrode 10, as shown in FIG. 3D.
Next, thermal oxidation is executed to form thermal oxide films 9a and 9b on the gate electrode 10 and source and drain region 5, as shown in FIG. 3E.
Then, with the gate electrode 10 and insulating spacer 7 used as masks, second impurity ions are injected into the substrate surface at a higher concentration than the first impurity ions to form an N.sup.+ type source and drain region 8c.
According to this prior art, however, at the time of patterning the polycide gate electrode 10 by dry etching, the gate oxide film 3 may be damaged, lowering the breakdown voltage of the gate oxide film 3. When the tungsten silicide film 12 is oxidized in the thermal oxidation step to protect the N.sup.- type source and drain region 5 which is exposed at the time of forming the insulating spacer 7, the tungsten oxide flies and is diffused in the oxide atmosphere to permeate in the thermal oxide film 9b on the N.sup.- type source and drain region 5, so that the tungsten oxide is diffused into the PN junction between the source and drain region 5 and the P type silicon semiconductor substrate 1 in the later heating step, thus increasing the leak current.